Different types of memory are used in electronic apparatus for various purposes. Read-Only Memory (ROM) and Random Access Memory (RAM) are two such types of memory commonly used within computers for different memory functions. ROM retains its stored data when power is switched off and therefore is often employed to store programs that are needed for initializing (colloquially, “booting up”) an apparatus. ROM, however, does not accommodate writing. RAM, on the other hand, allows data to be written to or read from selected addresses associated with memory cells and, therefore, is typically used during normal operation of the apparatus.
Two common types of RAM are dynamic RAM (DRAM) and static RAM (SRAM). DRAM is typically used for the main memory of computers or other electronic apparatuses since, though it must be refreshed, it is typically inexpensive and requires less chip space than SRAM. Though more expensive and space-consumptive, SRAM does not require refreshing thereby making it a faster memory option. In addition, SRAM may use metal-oxide-semiconductor (MOS) technology, allowing it to have a relatively low standby power. These attributes make SRAM devices particularly desirable for portable equipment, such as cellular telephones, laptop computers and personal digital assistants.
A typical SRAM device includes a matrix of addressable memory cells arranged in columns and rows and referred to as an SRAM array. A typical memory cell includes two access transistors and a flip-flop having two memory transistors and two loads. The gates of the access transistors in each row are connected to a wordline and the sources of each access transistor are connected to either one of a bitline pair, B or B. Peripheral circuitry associated with the rows (or wordlines) and peripheral circuitry associated with the columns (or bitlines) facilitate reading data from, and writing data to, the memory cells.
Generally, to read data from a memory cell, a wordline driver activates a wordline according to an address decoded by a row decoder and received via a row signal path that typically includes an address bus connected to the SRAM device. The access transistors turn on and connect the outputs of the flip-flop to the bitline pair sending signals representing the data in the memory cell to a sense amplifier coupled to the bitline pair that amplifies the potential difference thereon. After the data is stabilized, a column decoder selects the corresponding column, or bitline pair, and outputs a data signal to a data output buffer and then to the external circuitry of the associated electronic apparatus. Essentially, data may be written to each memory cell in an opposite way.
As mentioned above, to retain the data written to the matrix of memory cells, or memory array, each memory cell must have a continuous supply of power. SRAM devices, however, are often employed within battery-powered wireless apparatus where power consumption is an important design parameter. Accordingly, wireless apparatus may be transitioned from an active or idle mode to a standby mode of lower power consumption. As transistor size continues to diminish (e.g., 90 nm transistors), current leakage may be unacceptably high even during standby mode, requiring a transition to a still lower power consumption level, a data retention or sleep mode, to conserve power adequately. The battery-powered wireless apparatus, therefore, may power-down the row and column circuitry associated with the memory array and enter the sleep mode while still supplying sufficient power to the memory array to retain data.
Accessing data of a SRAM device in a standby mode, however, suffers due to time and energy required to transition from the standby mode to an active mode. Thus, even though standby modes reduce power consumption of the SRAM device, performance of the SRAM device is also reduced.
Accordingly, what is needed in the art is an improved high performance, low leakage SRAM device. More specifically, what is needed in the art is an improved SRAM device that minimizes leakage while still maintaining high performance during an active mode.